Methods and apparatus for tissue activation and monitoring

ABSTRACT

Techniques for controlling one or more modular circuits (“satellites”) that are intended for placement in a subject&#39;s body. The one or more satellites are controlled by sending signals over a bus that includes first and second conduction paths. Also coupled to the bus in system embodiments is a device such as a pacemaker that provides power and includes control circuitry. Each satellite includes satellite circuitry and one or more effectors that interact with the tissue. The satellite circuitry is coupled to the bus, and thus interfaces the controller to the one or more effectors, which may function as actuators, sensors, or both. The effectors may be electrodes that are used to introduce analog electrical signals (e.g., one or more pacing pulses) into the tissue in the local areas where the electrodes are positioned (e.g., heart muscles) or to sense analog signals (e.g., a propagating depolarization signal) within the tissue.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 from the followingprovisional applications:

-   -   U.S. Provisional Patent Application No. 60/707,995, filed Aug.        12, 2005, titled “Methods and Apparatus for Tissue Activation        and Monitoring” by inventor Mark Zdeblick;    -   U.S. Provisional Patent Application No. 60/679,625, filed May 9,        2005, titled “De Minimus Control Circuit for Cardiac Pacing and        Signal Collection” by inventor Mark Zdeblick;    -   U.S. Provisional Patent Application No. 60/638,928, filed Dec.        23, 2004, titled “Methods and Systems for Programming and        Controlling a Cardiac Pacing Device” by inventor Mark Zdeblick;        and    -   U.S. Provisional Patent Application No. 60/607,280, filed Sep.        2, 2004, titled “One Wire Medical Monitoring and Treating        Devices” by inventor Mark Zdeblick.

The entire disclosures (including any attachments or appendices) of theabove patent applications and those of the following commonly ownedpatent applications are hereby incorporated by reference for allpurposes:

-   -   U.S. patent application Ser. No. 10/764,127, filed Jan. 23,        2004, titled “Methods and Systems for Measuring Cardiac        Parameters” by inventors Mark Zdeblick and Joseph M. Ruggio        (published Dec. 16, 2004 as No. 20040254483);    -   U.S. patent application Ser. No. 10/764,429, filed Jan. 23,        2004, titled “Method and Apparatus for Enhancing Cardiac Pacing”        by inventors Mark Zdeblick and Joseph M. Ruggio (published Nov.        4, 2004 as No. 20040220637);    -   U.S. patent application Ser. No. 10/764,125, filed Jan. 23,        2004, titled “Method and System for remote Hemodynamic        Monitoring” by inventors Mark Zdeblick and Joseph M. Ruggio        (published Oct. 28, 2004 as No. 200402.15049); and    -   U.S. patent application Ser. No. 10/734,490, filed Dec. 11,        2003, titled “Method and System for Monitoring and Treating        Hemodynamic Parameters” by inventors Mark Zdeblick and George M.        Savage (published Sep. 30, 2004 as No. 20040193021).

BACKGROUND OF THE INVENTION

The present invention relates to administering electrical signals tolocal areas of living tissue and monitoring conditions in such tissue.In particular, the present invention relates to a low-power modularcircuit for controlling one or more electrodes that can be used toadminister or monitor such electrical signals.

Electrodes for administering electrical signals or for monitoringelectrical signals at specific locations in living tissue, such as theheart, are important tools used in many medical treatment or diagnosis.U.S. Pat. No. 6,473,653, entitled “Selective Activation of Electrodeswithin an Implantable Lead,” to Schallhorn et al., filed on Mar. 2,2000, discloses an implantable multi-electrode lead adapted to allowselective activation of the included electrodes to electrically excitethe tissue in the vicinities of the activated electrodes. U.S. Pat. No.5,593,430, entitled “Bus System for Interconnecting an ImplantableMedical Device with a Plurality of Sensors,” to Renger, filed on Jan.27, 1995, discloses a two-conductor bus system for connectingphysiologic sensors to a pacemaker. The two-conductor bus provides powerto the sensors, and the sensors' output signals are modulated on the twowires.

SUMMARY OF THE INVENTION

In broad terms, the invention provides methods and apparatus forcontrolling one or more modular circuits (“satellites” or “satelliteunits”) that are intended for placement in a subject's (typically, butnot necessarily, human) body. The one or more satellites are controlledby sending signals over a bus that includes first and second conductionpaths (usually referred to as bus conduction paths). Also coupled to thebus in system embodiments is a device such as a pacemaker that providespower and includes control circuitry. For convenience, this device willbe referred to as the central controller, although as will be seenbelow, it may itself be a distributed system.

Each satellite includes satellite circuitry and one or more devices thatinteract with the tissue. The satellite circuitry includes at least oneactive device, and is typically an integrated circuit (“satellitechip”). The satellite circuitry is coupled to the bus, and thusinterfaces the central controller to the one or more devices. Typically,the devices that interact with the body (“interacting devices” or“effectors”) may function as actuators (sometimes referred to asactivators), sensors, or both. For example, these effectors may beelectrodes that are used to introduce analog electrical signals (e.g.,one or more pacing pulses) into the living tissue in the local areaswhere the electrodes are positioned (e.g., heart muscles) or to senseanalog signals (e.g., a propagating depolarization signal) within theliving tissue.

The bus is typically used to carry analog and digital signals, and, atvarious times during operation, may be used to do one or more of thefollowing: transmit digital information from the central controller tothe satellites, send configuration information from the centralcontroller to the satellites to configure one or multiple effectorsassociated with selected satellites, provide a power supply to operatethe digital logic circuits within the satellite chip, transmitactivation pulses from the central controller to the satellites,transmit analog signals from the satellites to the central controller,and transmit digital signals (e.g., signals confirming theconfiguration) from the satellites to the central controller.

Some embodiments include one or more individually addressablesatellites, and the central controller is able to configure or otherwisecontrol one or more selected satellites. In such embodiments, the busmay be used to transmit address information from the central controllerto the satellites, send configuration information from the centralcontroller to the satellites to configure one or multiple effectorsassociated with selected satellites.

Different embodiments are characterized by different implementations ofthe first and second bus conduction paths, or portions thereof. In someembodiments, a bus conduction path is said to be insulated from thesubject's body. Such a conduction path includes a discrete conductiveelement (e.g., a wire; namely a dedicated conductor) that is distinctfrom the subject's body and an insulating material separating theconductive element from the subject's body. In this context, “insulated”should be taken to include the possibility that there may be smallleakage currents, but that efforts have been made to insulate theconduction path from the subject's tissue.

In other embodiments, a bus conduction path is not insulated from thesubject's body. Such a conduction path may include a discrete conductiveelement that is in contact with the subject's body, or may be defined bythe subject's body so that the conduction is through the subject'stissue and/or body fluids. In some embodiments, a conduction path(referred to as a hybrid conduction path) includes a portion that isinsulated from the subject's body and a portion that is not insulatedfrom the subject's body. The portion of the conduction path that is notinsulated can include a discrete conductive element in contact with thebody or can be defined by a portion of the subject's body, or caninclude both.

In some embodiments, at least one of the bus conduction paths isassociated with a carrier such as a pacing lead, and the satellites areplaced along the carrier. The satellite-bearing carrier is intended tobe implanted or otherwise inserted into tissue (e.g., the heart) so asto interact with the tissue.

As a result, a system based on embodiments of the present invention hassignificantly increased flexibility and accuracy, whether used foractivation or sensing. For example, in one embodiment, one carrieraccommodates eight satellites, each controlling four electrodes. Such aconfiguration allows the system to select, and activate or sense withvarious combinations of the 32 electrodes with a desired sequence.

Embodiments of the present invention include satellite chips thatconsume very little power. Thus, a satellite chip in some embodimentscan remain in a configured state for a long period of time without beingrecharged. In one embodiment, the satellite chip need only be rechargedafter a time interval exceeding 30 minutes and draws only a current inthe order of a few picoamps. To save power, the satellite chip storesthe satellite and electrode address and configuration information inregisters, and shuts off power for idle portions of the digitalcircuits. As a result of this low power capability, the satellites ofthe present invention may be easily incorporated into commercial pacingsystems.

The term “wire” is sometimes used for one of the bus conduction paths,and in some embodiments, the satellite chip contact terminal orterminals are bonded to a metal wire. However, the term “wire” should beinterpreted broadly to include non-metallic solid conducting orsemiconducting materials, and also channels filled with conductivepolymers, fluids, gels, pastes, and the like. In some instances, thesatellite chip terminal contacts will contact a conductive fluid or gel,which may itself contact another conductive solid material. Further,while metal electrodes are contemplated, other conductive materials(e.g., silicides) could be used.

In one set of embodiments, referred to as two-wire embodiments, thefirst and second bus conduction paths are insulated from each other andfrom the subject's body, and both are typically associated with thecarrier. In another set of embodiments, referred to as one-wireembodiments, one of the conduction paths is insulated from the subject'sbody, but the other is defined in part or whole by the subject's body.In a third set of embodiments, both conduction paths are defined inwhole or in part by the subject's body.

In one aspect of the invention a method for configuring one or moreeffectors situated within a satellite unit that resides in a subject'sbody includes: receiving signals over a bus; and based on the signalsreceived over the bus, deriving a relatively stable DC voltage forsupplying the circuitry, recovering clock and digital data, interpretingbit sequences in the digital data to extract configuration information,and using the bit sequences to store configuration information for theone or more desired effectors.

In another aspect of the invention, a medical apparatus includes: acarrier unit configured for insertion into a subject's body, a bushaving at least one conduction path, at least a part of which isinsulated from the subject's body when the carrier is inserted into thesubject's body, and a plurality of satellite units located along thecarrier aid connected to the bus. Each satellite unit includes one ormore effectors that interact with the subject's body when the carrier isinserted into the subject's body, and satellite circuitry that iscoupled to the bus. The satellite circuitry is structured to receivepower over the bus, receive a bit sequence over the bus, and storeinformation based on the bit sequence.

In another aspect of the invention, a method for controlling one or moresatellite units which reside along a carrier located in a subject's bodyincludes: supplying power to one or more of the satellite units over abus, transmitting a bit sequence over the bus, and storing informationin at least one satellite unit based on the bit sequence. The busincludes first and second conduction paths with at least the firstconduction path being insulated from the subject's body when the carrieris located within the subject's body.

In another aspect of the invention, a method for configuring one or moreeffectors situated within a satellite unit that resides along a carrierlocated in a subject's body includes: receiving signals over a bus; and,based on the signals received over the bus, deriving a relatively stableDC voltage for supplying the circuitry, recovering clock and digitaldata, interpreting bit sequences in the digital data to extract addressinformation, and at least for cases where the address informationmatches stored address information, using the bit sequences to configureone or more desired effectors to be coupled to the first or the secondconduction paths of the bus.

In another aspect of the invention, an integrated circuit for use toconfigure electrodes in an implanted lead includes: a first terminal; asecond terminal; and circuitry coupled to the first and second terminalswherein, during a first time interval, during which digitalconfiguration signals are provided from the controller on the firstterminal, the circuitry selectively configures selected ones of theelectrodes to the first terminal, and wherein, during a second timeinterval, the controller administers electrical signals through theconfigured electrodes by way of the first terminal.

In another aspect of the invention, a medical apparatus for interactingwith a body includes: a controller-power source with at least a firstelectrode (e.g., the outside conductive surface of the housing)contacting the body, a satellite unit for placement within the body, thesatellite unit including satellite circuitry connected to at least asecond electrode, the second electrode being in electrical contact withthe body; and a single conductor between the controller-power source andthe satellite unit, wherein data and power current flow from thecontroller-power source through the single conductor to said satelliteunit, through the second electrode, through the body, through the firstelectrode, and to the controller-power source.

A further understanding of the nature and advantages of the presentinvention may be realized by reference to the remaining portions of thespecification and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of an exemplary cardiac pacing and signaldetection system;

FIG. 2 is a high level block diagram of the communication between thecentral controller and a number of satellites, and also shows anexemplary satellite architecture;

FIG. 3 is an exemplary external view of a lead with several satellitesdisposed therealong, and also shows enlarged electrode details;

FIG. 4 is a timing diagram showing selected voltage traces of signals onthe bus and signals generated on the satellite chip;

FIG. 5 is a block diagram showing two portions, a satellite checkportion and a common portion, of an integrated circuit (“satellitechip”) in a satellite;

FIG. 6 is a functional block diagram of the common circuitry shown inFIG. 5, showing a data and clock recovery circuit, an initializationgeneration circuit, a command interpretation circuit, a power recoverycircuit, an electrode control circuit, and four electrode switch orelectrode pad (“EPAD”) circuits;

FIG. 7 is a schematic circuit diagram of an exemplary implementation ofthe data and clock recovery (DCR) circuit and the power recovery circuitshown in FIGS. 2 and 6;

FIG. 8 is a schematic circuit diagram of an exemplary implementation ofthe DCR circuit's local voltage generation circuit shown in FIG. 7;

FIG. 9 is a schematic circuit diagram of an exemplary implementation ofthe initialization generation circuit shown in FIGS. 2 and 6;

FIG. 10 is a schematic circuit diagram of an exemplary implementation ofthe command interpretation circuit shown in FIGS. 2 and 6;

FIG. 11 is a functional block diagram of an exemplary electrode controlcircuit that includes two electrode register circuits and four electrodedriver circuits;

FIG. 12 is a schematic circuit diagram of an exemplary implementation ofany one of the electrode register circuits shown in FIG. 11;

FIG. 13 is a schematic circuit diagram of an exemplary implementation ofany one of the electrode driver circuits shown in FIG. 11;

FIG. 14 is a schematic circuit diagram of an exemplary implementation ofone of the electrode pad (EPAD) circuits shown in FIG. 6;

FIG. 15 is a flow chart illustrating an exemplary configuration(programming) process followed by a cardiac pacing or monitoringprocess; and

FIG. 16A is a schematic representation of programming and pacing with atwo-wire embodiment of the invention;

FIG. 16B is a schematic representation of programming and pacing with atwo-wire embodiment of the invention;

FIG. 17 is a block diagram of an embodiment of a satellite that receivesAC voltages;

FIG. 18 is a timing diagram showing how to modulate the AC signal sentto the satellite; and

FIG. 19 is a block diagram showing the satellite of FIG. 17 in a systemwith hybrid bus conduction paths.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Introduction

The following description is presented to enable any person skilled inthe art to make and use the invention, and is provided in the context ofa particular application and its requirements. Various modifications tothe disclosed embodiments will be readily apparent to those skilled inthe art, and unless stated otherwise, the embodiments described shouldbe considered exemplary.

In broad terms, the invention provides embodiments where one or moreindividually addressable modular circuits (“satellites” or “satelliteunits”) are placed along a bus that includes at least one conductorassociated with a carrier such as a pacing lead. The bus provides firstand second conduction paths. In some embodiments (“two-wireembodiments), as will be described below, both conduction paths areinsulated from the subject's body. In other embodiments (“one-wireembodiments), only one of the conduction paths is insulated from thesubject's body while the other conduction path is provided by theconductive fluids in the subject's body.

In either case, the satellite-bearing carrier is intended to beimplanted or otherwise inserted into tissue (e.g., the heart) so as tointeract with the tissue. Each satellite includes satellite circuitryand one or more devices (“effectors”) that interact with the tissue. Inmany of the specific embodiments, these effectors are electrodes, andfor a cardiac application, they are used for pacing or sensing or both.

In the present application, terms such as “detecting” and “sensing” areused broadly. For example, consider where the satellite is configured touse a pair of its electrodes, which are in contact with the tissue, tomake a measurement or determine when a specific condition is met (e.g.,to detect a voltage change that signifies a depolarization signal).

In one set of embodiments, the satellite is configured to couple one ormore desired electrodes to the bus so the central controller can sensethe analog voltage that appears across the electrodes. The centralcontroller performs those operations required to determine, based on theanalog signal, if and when the condition has occurred, for example bydetermining that the voltage has exceeded a threshold (or met some otherset of conditions) during the interval that the satellite has itselectrodes coupled to the bus. In another set of embodiments, notspecifically described, the satellite could include additional circuitryso that the satellite, in addition to experiencing the voltages, coulddetermine when the analog voltage across its electrodes is such as toimply that the condition has been met, and could report such adetermination to the central controller using the bus.

In both these sets of embodiments, the satellite can be considered tohave detected the condition, although the central controller performsportions of the detection in the first set of embodiments. Thesecond-mentioned set of embodiments require more functionality on thepart of the satellite, for example, the ability to convert analogvoltages to digital signals, and to transmit digital signals.

Although the strict definition of electric current considers thedirection of current flow to be the direction in which positive chargesflow, it is not intended in the present application to limit thedirection that way. In other words, unless the context requiresotherwise, a statement that current flows from one point to another doesnot imply a particular direction in which positive charges flow.

In the most comprehensive system operation, the satellites are insertedin a subject's body, and communicate with a central controller. However,subsystems have commercial and medical viability. For example,components for pacing may be implanted during an initial surgery, butnot activated until needed, perhaps years later. When the subject isalready undergoing heart surgery, implanting some of the components atthat time tends to be much less invasive than implanting them later,especially after scar tissue arising from the surgery has formed. Evenif the subject is not in need of pacing, the components may be activatedfor monitoring purposes, and later activated for pacing purposes if andwhen a need is found. Indeed, it may be advantageous to implant atwo-dimensional mesh of satellites at the time of the surgery, even ifnone of the satellites are to be activated until later.

Location of Satellites for Cardiac Pacing or Signal Detection

FIG. 1 is a high level schematic of a cardiac pacing and signaldetection system in which a number of satellite units (or satellites)are disposed on one or more pacing leads and communicate with a pacingand detection controller 10, typically referred to as the centralcontroller. Central controller 10 provides extra-cardiac communicationand control elements for the overall system of FIG. 1, and may include,for example, a pacing can of a pacemaker, typically implanted under asubject's skin away from the heart. In the specific configurationillustrated, there are three pacing leads, including a right ventricularlead 12 and a left ventricular lead 15.

Right ventricular lead 12 emerges from the central controller, andtravels from the subcutaneous location of the central controller intothe subject's body (e.g., preferably, a subclavian venous access), andthrough the superior vena cava into the right atrium. From the rightatrium, right ventricular lead 12 is threaded through the tricuspidvalve to a location along the walls of the right ventricle. The distalportion of right ventricular lead 12 is preferably located along theintra-ventricular septum, terminating with fixation in the rightventricular apex. Right ventricular lead 12 is shown as havingsatellites 20 a, 20 b, 20 c, and 20 d. In one optional configuration,satellite 20 a includes a pressure sensor in the right ventricle.

Similarly, left ventricular lead 15 emerges from central controller 10,following substantially the same route as right ventricular lead 12(e.g., through the subclavian venous access and the superior vena cavainto the right atrium). In the right atrium, left ventricular lead 15 isthreaded through the coronary sinus around the posterior wall of theheart in a cardiac vein draining into the coronary sinus. Leftventricular lead 15 is provided laterally along the walls of the leftventricle, which is a likely position to be advantageous forbi-ventricular pacing. Left ventricular lead 15 is shown as havingsatellites 25 a, 25 b, and 25 c.

The number of satellites shown is but one example. In some embodiments,there may be more; in others, fewer. The particular implementationdescribed below allows a large number of individually addressablesatellites. A typical embodiment may provide four electrodes persatellite and eight satellites per lead. A signal multiplexingarrangement, according to embodiments of the present invention,facilitates including active devices (e.g., pressure sensor 20 a) to alead for pacing and signal collection purposes (e.g., right ventricularlead 12). As mentioned above and described below in detail, theelectrodes controlled by the satellites may be used for pacing, and mayalso be used to detect analog signals, such as local analog cardiacdepolarization signals.

Central Controller Overview

Central controller 10 is shown in an enlarged detail to be a distributedsystem, where multiplexing and switching capabilities are provided by aswitching circuit 30 that augments a pacemaker 35 (commonly referred toas a pacemaker “can”), which may be any conventional pacemaker. Theswitching circuit acts as an interface between the pacemaker and aplurality of leads, designated L1 . . . Ln. Right and left ventricularleads 12 and 15 are examples of such leads, which are configured forplacement within the heart in an arrangement and by procedures wellknown by those skilled in the art. The arrangement described above withrespect to leads 12 and 15 is representative.

Switching circuit 30 may be housed within a can similar to that ofpacemaker 35, which housing is configured for implantation in thesubject adjacent to pacemaker 30. Switching circuit 30 is electricallycoupled to pacemaker 30 via a pair of signal lines, which are referencedherein as S1 and S2, wherein S1 represents ground and S2 is a voltagesupply. These lines may be configured at the pacemaker end in the formof a connector which can be plugged into standard pacemaker lead plugreceptors.

Central controller 10 performs a number of functions, which will beoutlined here. The precise division of labor between switching circuit30 and pacemaker 35 can be a matter of design choice. To the extent thatit is desired to implement embodiments of the present invention, thepacemaker can be considered to provide a power supply and the ability togenerate pacing pulses of desired voltage and duration. For purposes ofthis discussion, switching circuit 30 will be described as providing theadditional functionality. This is not critical, and indeed the pacemakerand the switching circuit can be implemented within a single housing.

In short, switching circuit 30 multiplexes the pacemaker signals amongthe various leads, although some signals may go to multiple leads. Theswitching circuit also sends signals to, and receives signals from, thesatellites on the bus. At various times, the switching circuit may beused to transmit address information from the central controller to thesatellites, send configuration information from the central controllerto the satellites to configure one or multiple electrodes associatedwith selected satellites, provide power to operate the digital logiccircuits within the satellite chip, transmit activation pulses from thepacemaker to the satellites, receive analog signals from the satellites,and receive digital signals (e.g., signals confirming the configuration)from the satellites.

Additionally, switching circuit 30 provides a communication link toexternal devices, such as a programmer 40, which can remotely controland program the switching circuit with operating or functionalparameters, certain parameters of which can then be communicated topacemaker 35 by the switching circuit. While any mode of telemetry maybe used to transfer data between switching circuit 30 and programmer 40,one suitable mechanism for use with implantable devices iselectromagnetic coils, where one coil is provided in switching circuit30 and another is provided in programmer 40. By placing the programmerin close proximity to the subject's chest in the vicinity of theimplanted switching can, telemetric communication can be established.

Information transmitted between switching circuit 30 and programmer 40is in the form of AC signals which are demodulated to extract a bitstream representing the digital information to be communicated. Thesignal(s) transmitted by programmer 40 and received by switching circuit30 provides a series of commands for setting the system operatingparameters. Such operating or functional parameters may include, but arenot limited to, assignment of the electrode states, the pulse width,amplitude, polarity, duty cycle and duration of a pacing signal, thenumber of pulses per heart cycle, and the timing of the pulses deliveredby the various active electrodes.

The AC signals sent from the programmer to the switching circuit canalso provide a system operating current which can be used to power upthe circuit components. To this end, the switching circuit can beprovided with a rectifier bridge and a capacitor. In typical situations,the switching circuit gets its power from pacemaker 35, but could beprovided with a separate battery if desired.

In addition to downloading information from a programming device, theswitching circuit may also be configured to upload information such assensing data collected and stored within a memory element of theswitching circuit. Such sensing data may include, but is not limited to,blood pressure, blood volume, blood flow velocity, blood oxygenconcentration, blood carbon dioxide concentration, wall stress, wallthickness, force, electric charge, electric current and electricconductivity.

The switching circuit may also be capable of storing and transmittingdata such as cardiac performance parameters, which are calculated by itor the pacemaker from the sensed data. Such cardiac performanceparameters may include, but are not limited to, ejection fraction,cardiac output, cardiac index, stroke volume, stroke volume index,pressure reserve, volume reserve, cardiac reserve, cardiac reserveindex, stroke reserve index, myocardial work, myocardial work index,myocardial reserve, myocardial reserve index, stroke work, stroke workindex, stroke work reserve, stroke work reserve index, systolic ejectionperiod, stroke power, stroke power reserve, stroke power reserve index,myocardial power, myocardial power index, myocardial power reserve,myocardial power reserve index, myocardial power requirement, ejectioncontractility, cardiac efficiency, cardiac amplification, valvulargradient, valvular gradient reserve, valvular area, valvular areareserve, valvular regurgitation, valvular regurgitation reserve, apattern of electrical emission by the heart, and a ratio of carbondioxide to oxygen within the blood.

Switching circuit 30 may also function as part of a satellite powermanagement system. As will be described in greater detail below, eachsatellite has a capacitor that stores sufficient charge to power certainparts of the satellite circuitry (e.g., latches storing satelliteconfiguration information) when power is not being provided over thebus. While leakage currents may be extremely low, and normal signalingand pacing may provide enough power to keep the capacitor charged,switching circuit may be configured to periodically supply asufficiently high voltage pulse for a few microseconds, possibly from 10to 20 microseconds, to recharge all the satellite capacitors.Additionally, switching circuit 30 can be programmed to periodically,e.g., once daily, refresh the then current satellite configuration thathad been stored memory. In case of a power glitch which disrupts theelectrode status, switching circuit 30 can reset the electrodecapacitors to the last configuration stored in memory.

Another function which may be performed by switching circuit 30 is thatof transmitting analog signals from the satellites to pacemaker 35. Forexample, where the pacemaker is attempting to sample voltages at aplurality of locations within the heart in order to generate a map ofthe heart's electrical potentials, switching circuit 30 enables this byproviding high-speed switching between the electrodes selected for thevoltage sampling. More specifically, over a very short time period, onthe order of milliseconds, the electrical potential at a selectedelectrode is sampled, information regarding the analog voltage is sentto pacemaker 35, and the sequence is repeated for another selectedelectrode. The faster the switching, the more accurate the “snap shot”of potentials is at various locations about the heart, and thus, themore accurate the electrical potential map.

In some embodiments, the information regarding the analog voltage is theanalog signal itself. That is, the measured potentials are provided asanalog signals which are carried from the satellite electrodes topacemaker 35 by way of switching circuit 30 where the signal from oneelectrode is provided on line S1 and the signal from another electrodeis provided on line S2. An amplifier or voltage comparator circuitwithin pacemaker 35 may then compare the two analog voltages signals.Based on this comparison, pacemaker 35 will reconfigure the pacingparameters as necessary. Alternatively, each satellite chip couldinclude an analog-to-digital converter that digitizes the analog voltagesignal prior to sending it to switching circuit 30. It is believed thatproviding this additional functionality in the satellites would requirelarger satellite chips, would be more power consumptive, and would beslower since the time necessary for the charges on the capacitors in thesatellites to settle and become balanced would be far greater. Thus,this approach is not preferred.

Still yet, switching circuit 30 may function as an analog-to-digital anddigital-to-analog conversion system. A sensing protocol, eitherprogrammed within switching circuit 30 or otherwise transmitted by anexternal program by programmer 40, in the form of digital signals isconverted to an AC signal by switching circuit 30. These analog signalsinclude current signals which drive sensing electrodes or other types ofsensors, e.g., transducers, to enable them to measure physiological,chemical and mechanical signals, e.g., conductance signals, within thesubject's body. The measured signals, also in analog form, are thenconverted to digital signals by switching circuit 30 and stored inmemory, used to calculate other parameters by the switching circuit ortransmitted to pacemaker 35 and/or programmer 40 for further processing.

A multiple electrode lead allows for greater flexibility in leadplacement as at least one of the multiple electrodes will be optimallypositioned to pace the heart. Determining which of a lead's electrodesis best positioned to obtain or provide an accurate signal to and formthe heart may be determined experimentally by controlled pacing of theheart and measuring the resulting threshold voltage of each electrode,wherein the electrode with the lowest threshold voltage is the mostoptimally positioned electrode for that satellite unit. Additionally,the electrode facing away from a nearby nerve may be preferred. Forexample, stimulation of the phrenic nerve can cause hiccups.

Once the electrode on each satellite unit with the lowest threshold orleast sensitive to phrenic nerve stimulation is established, then thevarious satellite units may be selected one at a time or in combinationsto determine which satellite unit(s) with its best electrodeconfiguration produces the best hemodynamic response. This latteroptimization may be performed with feedback from an external device suchas an ultrasound system, or with one of the other feedback systemsreferenced in the above published applications.

System Architecture and Satellite Overview

FIG. 2 is a high level block diagram of the communication betweencentral controller 10 and a number of satellites, designated 20 a, 20 b,. . . as suggesting these to be the satellites on right ventricular lead12. Successively enlarged first- and second-level detail views show anexemplary satellite architecture. This figure shows the bus andsatellites corresponding to a single lead, it being understood thatsimilar view could be presented for other leads. As mentioned above,switching circuit 30 can multiplex and switch between leads.

The figure shows central controller communicating with the satellitesover a bus 50, which is seen to have first and second conduction pathsS1 and S2. As seen in the first-level detail view, the satelliteincludes satellite circuitry 60, typically an integrated circuit(“satellite chip”) and a number of effectors 65 that interact with thetissue in which the satellites are implanted or otherwise inserted.Effectors 65 may function as actuators, sensors, or both. In manyembodiments, the effectors are electrodes, and in much of the discussionthat follows, effectors 65 will often be referred to as electrodes. Itshould be kept in mind, however, that they can be other types ofactuators or sensors.

The satellite chip is shown as having two terminals S1 and S2,corresponding to the bus conduction paths. In a particularimplementation, S1 is ground and S2 varies depending on the particularoperation being performed, but a maximum DC voltage of 5 volts istypical. Also, while the figure shows bus conduction paths S1 and S2 asif they are wires, conduction path S2 is provided by the subject's bodyin the one-wire embodiments.

The second-level detail view shows the basic elements of the satellitechip in a representative embodiment. These basic elements include a dataand clock recovery (DCR) circuit 70, an initialization generationcircuit 75, a command interpretation circuit 80, electrode registers orlatches 85 for storing electrode configuration information, an electrodedriver and switch circuit 90, and a power recovery circuit 95. Powerrecovery circuit 95 includes a diode 97 (implemented as adiode-connected NMOS transistor in an exemplary implementation) and acapacitor 98 that stores sufficient charge to maintain certain portionsof the satellite circuitry (e.g., stored configuration information) forsignificant periods of time when the satellite is not deriving powerfrom the bus. The voltage on capacitor 98 is designated “vhigh.”

In the second-level detail view, effectors 65 of the first-level detailviews are shown specifically as four electrodes 100 a, 100 b, 100 c, 100d. As noted above, the invention is not limited to the effectors beingelectrodes, and further the invention is not limited to a specificnumber of effectors associated with a given satellite. Indeed, in someembodiments different satellites can have different numbers ofeffectors, especially if some of the satellites have differentspecialized effectors.

While the highest-level shows the bus as linear, as for example would bethe case for satellites disposed along a pacing lead, the satellitescould be disposed in a two-dimensional array on a mesh. This isespecially practical with one-wire embodiments. This possibility isillustrated with an additional detail view.

FIG. 3 is an exemplary external view of a lead, say right ventricularlead 12, with several satellites, again denoted 20 a, 20 b, . . . ,disposed therealong. The figure also includes an enlarged detail view ofan exemplary electrode configuration for two-wire and one-wireembodiments. The two-wire embodiment is on the left of the detail view,the one-wire embodiment on the right. In this embodiment, the satellitesare cylindrical, and at least for the two-wire embodiment are providedwith four electrodes, again designated 100 a, 100 b, 100 c, and 100 d,configured in the four quadrants of the cylindrical outer walls ofsatellite 20 a. The satellite chip is embedded inside the cylinder andis not shown in this figure. Bus conduction paths S1 and S2 pass throughthe region between the electrodes and are coupled electrically to the S1and S2 terminals of the satellite chip. The satellite chips in thesatellites receive signals over the bus, which in an exemplaryembodiment include address information specifying a given satellite andconfiguration information specifying which, if any, of electrodes 100 a. . . 100 d are to be coupled to bus conduction paths S1 or S2.

Although shown in a cylindrical arrangement, electrodes 100 a . . . 100d may be offset along lead 12 to minimize capacitive coupling amongthese electrodes, if desired. The quadrant arrangement of electrodesallows administering pacing current via electrodes oriented at apreferred direction (e.g., away from nerves, or facing an electrodeconfigured to sink the pacing current). Such precise administration ofpacing current allows low-power pacing and minimize tissue damage due tothe pacing signal.

In the one-wire embodiment, there is only one explicit conduction paththat is insulated from the subject's body, namely S1, and the conductivefluids in the subject's body tissues provide the second conduction pathS2 (not explicitly shown). In one implementation of a one-wiresatellite, a fifth electrode 105 is coupled to the satellite chip's S2terminal. As described in greater detail below, one of the otherelectrodes can be used for this purpose.

Representative Timing Diagram

FIG. 4 is a timing diagram showing selected voltage traces of signals onthe bus and signals generated by DCR circuit 70 in the satellite chip.These voltages are designated “Vs2,” “Vinm,” “vhigh,” “vref,” and“Vdata_cap.” As mentioned above in connection with FIG. 2, “vhigh” is avoltage stored on capacitor 98 in power recovery circuit 95, beingoriginally derived from the voltage on bus conduction path S2. As willbe described in greater detail with reference to FIGS. 7 and 8, DCRcircuit 70 includes a local voltage generation circuit 110 andcomparators 112 and 115. The DCR circuit's local voltage generationcircuit provides a series of voltages “vdcr,” “vpbias,” “vnbias,” and“vref” that are used in the DCR circuit.

More specifically, FIG. 4 shows the result when a DC voltage is suppliedon bus 50 and then modulated to communicate data to the satellites. Anysuitable modulation regime can be used, such as phase-shift-keying(PSK), frequency-shift keying (FSK), or return-to-zero (RZ), to name afew. In the particular implementation, a data bit is represented by onecycle of a square wave, with a logical “1” having twice the period(represented by a 1-μs cycle) of a logical “0” (represented by a 0.5-μscycle). This is akin to a type of frequency shift keying (FSK) since thefrequency of the square wave differs for the two possible bit values.

The figure shows a particular sequence of bit values encoded as amodulation of the bus voltage, and the voltages generated on thesatellite chip to extract these data values. As mentioned above, in aparticular implementation, the first conduction path S1 is ground, andtherefore the voltages and signals on the chip are generally derivedfrom the voltage on the second conduction path S2.

“Vs2” is the voltage seen by the satellite chip's circuitry by virtue ofthe voltage on bus conduction path S2. In two-wire configurations, thisis the voltage on conduction path S2; in at least some one-wireconfigurations, it is a diode drop below the potential at an electrodethat contacts a biologic conductor (tissue or blood). FIG. 2, as well asa number of figures containing circuit schematics discussed below, use anode label “S2” to represent a coupling to bus conduction path S2. Inview of the possibility that the voltage seen at this node might be adiode drop below the value of the voltage on bus conductor these nodelabels should be read generally to mean “vS2.”

“Vinm” is a signal that represents the near-term average of “Vs2.”“Vinm” and “Vs2” are the inputs to comparator 112, and are used toproduce the clock signal. “vref” is one of the signals generated by theDCR circuit's local voltage generation circuit 110, and is used inconnection with the data recovery. To determine the data value, theclock signal is then used to generate a ramp voltage (“Vdata_cap”) whichis compared to “vref” by comparator 115. If “Vdata_cap” is greater than“vref,” the output of comparator 115 becomes a logical “1.”

According to some embodiments of the present invention, signalcommunication on the bus may be conducted in one or more of threephases, namely a configuration phase, a pacing (or other activation)phase, and a signal collection (monitoring) phase. During aconfiguration phase, central controller 10 sends configuration signalsto specify which satellite or satellites to activate and whichelectrodes on each activated satellite are to be coupled to which busconduction path (i.e., S1 or S2). The configuration signals, whichinclude various addresses and control commands, are provided to allsatellites over bus conduction paths S1 and S2. These configurationsignals are communicated by modulating the voltage between busconduction paths S1 and S2, and in the particular implementation themodulation comprises 0.5 volt peak-to-peak digital pulses on a 5-volt DCsignal. This is shown in FIG. 4 as a modulation of signal.

By way of the example shown in FIG. 4, after an initial time interval of20 microseconds, during which the signals “Vs2,” “vref,” and “vhigh”(which are explained in the description corresponding to FIG. 7) areallowed to stabilize, octets “00000000”, “00100000” and “00011011” aretransmitted with an embedded clock signal (“clk”) on bus conduction pathS2 (relative to the “ground voltage” of bus conduction path S1). Inresponse, a selected satellite stores the configuration information inits registers and prepares its electrodes to be used for the subsequentpacing or signal collection operations. After the configuration phase(i.e., after the specified satellites are activated and the specifiedelectrodes are coupled to their respective bus conduction paths, orremain disconnected), central controller 10 may initiate a pacing phaseor a signal collection phase.

In a pacing phase, central controller 10 sends pacing signals on the busby generating suitable potential differences between the bus conductionpaths. In the pacing phase, pacing occurs at specified configuredelectrodes to the tissue in their vicinities. Therefore, pacing pulsesare delivered during the pacing phase directly and precisely to selectedtissue locations.

In a signal collection phase, bus conduction paths S1 and S2 may beallowed to float, so as to conduct analog signals detected by theconfigured electrodes to central controller 10. Furthermore, theconfigured electrodes retain their respective configured states (i.e.,coupled to or de-coupled from a bus conduction path). Because of the lowpower consumption of the satellite chips, frequent refreshing of theirconfigurations are not required.

In the two-wire embodiments, the digital control (e.g., configuration)signals and the sensed analog signals are communicated along busconduction paths S1 and S2. Since both digital and analog signals arecommunicated along bus conduction paths S1 and S2, it is not necessaryto provide the satellites with digital-to-analog or analog-to-digitalconverters. This reduces the power consumption of the chip, althoughthere may be applications where such conversion circuitry could beprovided for special, possibly infrequent use.

In the two-wire embodiments, pacing pulse signals may be applied to thededicated bus conduction paths S1 and S2, and the voltage applied to thesubject's tissue between selected electrodes, either on the samesatellite, or on different satellites. However, there are somesituations where the pacing voltage would be applied between a selectedelectrode on a selected satellite and the pacemaker can. While thestimulation provided in this regime is not as localized, it has theadvantage that the pacemaker can provides a larger surface than would beprovided by a second electrode, thereby reducing the incidence ofcorrosion.

In one-wire embodiments, where bus conduction path S2 is the subject'sbody, the digital signals and the pacing signals are communicatedthrough the subject's body.

Satellite Circuitry Overview

FIG. 5 is a block diagram of an exemplary embodiment of satellitecircuitry 60, as implemented in a satellite chip. As shown in FIG. 5,the satellite chip includes a common circuit 120, which is usually thesame for a plurality of satellites, and a satellite-check circuit 125,which is usually different for each satellite. According to oneembodiment, common circuit 120 is coupled to bus conduction paths S1 andS2 and is provided identically in each satellite. Common circuit 120carries out such functions as deriving power supply signal “vhigh,”recovering a clock signal (provided as a pair of complementary clocksignals “clk” and “clkb”) and data bits from signal “Vs2,” decodingaddress signals and control commands, and configuring the electrodes.Common circuit 120 provides decoded address bits serially tosatellite-check circuit 125 as a serial output signal“serialcommon_out.”

Satellite-check circuit 125 maintains the satellite's unique identityinformation (address), which is typically hard coded in the chip. Itcompares the address bits received from common circuit 120 to its storedidentity information to derive control signals “iamit1” and “iamit2,”which indicate whether or not the received address bits match theidentity information stored in satellite-check circuit 125. As describedbelow, control signals “iamit1” and “iamit2” are used to deriveconfiguration signals to configure the electrodes in a satellite forsubsequent pacing or signal detection phases.

In one embodiment of the present invention, the functions of a satellitechip mentioned above are carried out by customized digital circuits(combinatorial logic) rather than by executing software or firmware.This approach provides the advantages of low-power operation and fastresponse time.

FIG. 6 is a functional block diagram of an implementation of commoncircuit 120 of FIG. 5, showing in greater detail the communication amongthe blocks in FIG. 2. As shown for this implementation, common circuit120 includes data and clock recovery (DCR) circuit 70, initializationgeneration circuit 75, command interpretation circuit 80, and powerrecovery circuit 95. The figure also shows a circuit denoted aselectrode control circuit 130 and four circuits denoted as electrodeswitch or electrode pad (“EPAD”) circuits 135 a, 135 b, 135 c, and 135d. Electrode control circuit 130 and EPAD circuits 135 a, 135 b, 135 c,and 135 d provide the functionality of electrode registers 85 andelectrode driver and switch circuit 90 shown in FIG. 2.

DCR circuit 70 derives and recovers complementary clock signals “clk”and “clkb”, and a digital data signal “dcr_out” from the voltage acrossbus conduction paths S1 and S2. Signal “dcr_out” is a digital signalusing 0 volts and voltage “vhigh” to encode logic states of the outputbits. DCR circuit 70 also receives complementary sleep signals“dcrsleep” and “dcrsleep_b,” which turn off DCR circuit 70 at times whenthere are no data or clock signals that need to be recovered from thebus, such as during pacing and signal collection phases, or when thesatellite has determined that it is not being addressed by digitalsignals on the bus. Power recovery circuit 95, drawn schematically aspart of the same block as DCR circuit 70, derives and recovers the powersupply voltage “vhigh” from the voltage across bus conductors S1 and S2.This supply voltage is used to operate the digital circuits in thesatellite chip.

Initialization generation circuit 75 derives initialization signals“s2_oneshot_b” and “vhigh_oneshot_b” from the voltage across busconduction paths S1 and S2. These initialization signals are assertedwhen “Vs2” and signal “vhigh” rise above their respective predeterminedvoltage thresholds.

Command interpretation circuit 80 receives the bits in digital datasignal “dcr_out” from DCR circuit 70 and maps these bits to controlcommands. Based on these control commands, it generates control signalsdesignated “switch” for effectuating the configurations specified forthe electrodes, “clearb_latch” for clearing the registers storing theconfigurations of the electrodes in electrode control circuit 130, and“dcrsleep” and “dcrsleep_b” for turning off DCR circuit 70. Commandinterpretation circuit 80 also provides the decoded data bits “bit15”(delayed by 16 clock periods) of serial data signal “dcr_out” toelectrode control circuit 130. When signal “s2_oneshot_b” is asserted,command interpretation circuit 80 de-asserts signal “dcrsleep” to wakeup DCR circuit 70. When “vhigh_oneshot_b” is asserted, commandinterpretation circuit 80 asserts signal “clearb_latch” to reset theconfiguration of the electrodes.

Electrode control circuit 130 receives control signals “switch,”“clearb_latch,” and “bit15” from command interpretation circuit 80, andcontrol signals “iamit1” and “iamit2” from satellite-check circuit 125,and uses these control signals to identify and configure the electrodes.Electrode control circuit provides output signals “s2 c_p_i,” “s2c_n_i,” and “s1 c_n_i” of electrode control circuit 130 are provided toeach of four EPAD circuits 135 a, 135 b, 135 c, and 135 d (where i is aninteger between 0 and 3, inclusive, identifying a corresponding EPADcircuit). Based on the three control signals received, each EPAD circuitis configured to couple to at most one of bus conduction paths S1 andS2. Electrode control circuit 130 provides the serial data bits tosatellite-check circuit 125 as signal “serialcommon_out.”

Power Recovery Circuit 95

The lower portion of FIG. 7 is a schematic circuit diagram of anexemplary implementation of power recovery circuit 95. As mentionedabove in connection with FIG. 2, power recovery circuit includesdiode-connected NMOS transistor 97, which charges capacitor 98 toprovide power supply voltage “vhigh,” which is used as a high-voltagepower supply voltage throughout the satellite chip. In one embodiment ofthe present invention, the capacitance of capacitor 98 is provided to begreater than about 1200 pF. Note that, as shown in FIG. 4, because ofthe modulation imposed upon the 5V DC voltage on bus conduction path S2,and because of the voltage drop over diode-connected NMOS transistor 97,power supply voltage “vhigh” is typically lower than 5V.

The present invention also obviates the need for high power dissipationcircuits such as A/D and D/A converters. In particular, sleep states areimplemented in those logic circuits which are inactive during pacing anddata collection phases, or during those intervals where no voltage isbeing applied to the bus. Hence, the amount of leakage current in thesatellite chip is very small. Consequently, power supply voltage “vhigh”needs not be refreshed for long periods of time. In one embodiment,power supply voltage “vhigh” needs not be refreshed more frequently thanonce every 30 minutes, drawing a current of a few picoamps, so that theresulting power dissipation of the satellite chip is less than a fewpicowatts. Power supply voltage “vhigh” is used to maintain the statesof the registers storing the electrode configurations during those timeswhen the satellite chip is not getting power over the bus.

Data and Clock Recovery (DCR) Circuit 70

The upper portion of FIG. 7 is a schematic circuit diagram of anexemplary implementation of DCR circuit 70. As mentioned above inconnection with FIG. 4, the DCR circuit includes a local voltagegeneration circuit 110 and comparators 112 and 115. The DCR circuit'slocal voltage generation circuit provides a series of voltages “vdcr,”“vpbias,” “vnbias,” and “vref” that are used in other portions of theDCR circuit. The DCR circuit's local voltage generation circuit will bedescribed in greater detail below with reference to FIG. 8.

Comparator 112 recovers clock signals “clk” and “clkb” from “Vs2” andsignal “Vinm.” Signal “Vinm,” which is generated by a diode-connectedPMOS transistor 140 charging a capacitor 142, represents the averagevalue of “Vs2” and has a value substantially between 4.5V and 5V. In oneembodiment of the present invention, the capacitance of capacitor 142 isabout 5 pF. Because both input signals to comparator 112 are at voltagelevels close to 5V, comparator 112 is provided bias voltage “vnbias”which is generated in DCR circuit's local voltage generation circuit 10,shown in detail in FIG. 8.

In view of the nature of the inputs to comparator 112, its output signal“outm” has a time-sequence of pulses corresponding to the modulateddigital signal carried on the bus (corresponding to “Vs2′″). A set ofbuffers 150, powered by voltage “vhigh” and referenced to the voltage onbus conduction path S1, provide stable output clock signals “clk” and“clkb,” each having a peak-to-peak voltage close to 5 volts. Asmentioned above, output clock signals “clk” and “clkb” are distributedthroughout the satellite chip as system clock signals. The embedded FSKmodulated data signal results in a non-uniform duty-cycle for clocksignals “clk” and “clkb.”

Output signal “outm” is also buffered by a set of buffers 152. Theoutput signal of buffers 152 drives an NMOS transistor 155. Supplyvoltage “vdcr” charges a capacitor 160 through a PMOS transistor 162,but NMOS transistor 155 discharges capacitor 160 at each falling edge ofsignal “outm.” When supply voltage “vdcr” charges capacitor 160, signal“Vdata_cap” on capacitor 160 increases linearly before falling back tozero volts at the falling edge. The capacitance of capacitor 160 ischosen such that signal “Vdata_cap” does not exceed reference voltage“vref” during a 0.5-μs cycle (representing logic value “0”), but exceedsreference voltage “vref” during a 1-μs cycle (representing logic value“1”).

Thus, by comparing signal “Vdata_cap” with reference voltage “vref,”which is selected to be between 2.0 volts and 3.0 volts, as shown inFIG. 4, comparator 115 decodes the data bits embedded in signal “Vs2.”The decoded bits in the bit sequence are each captured by a flip-flop165 at the falling edge of each cycle. Because of the time required forthe integration, a one-cycle delay exists between the beginning of thecorresponding modulation period for any bit and the time at whichdecoding for that bit completes.

The negative input signal “Vinm” of comparator 112 decreases from 5V atthe beginning of the modulation, but remains approximately at the middlepoint between 4.5 V and 5 V after the first octet. Hence, comparator 112is able to generate an accurate clock signal by comparing signal “Vinm”as a reference signal against “Vs2.” Accordingly, it is preferred tosend an octet of all zeros before relying on the value of “Vinm” as areference for the clock and data signals. When power from the bus iswithdrawn (i.e., “Vs2” goes to zero), the state of flip-flop 155 ispreserved, “clk” remains at “vhigh,” and “clk” remains at zero since theflip-flop and buffers 150 are powered by “vhigh.”

The particular FSK-like modulation regime has the property that thewaveform for a “1” bit has twice the area as the waveform for the “0”bit and thus charges capacitor 160 above threshold only for the “1” bit.However, the regime does result in non-uniform clock cycles. Onealternative modulation regime that would also work for the samecircuitry but provide a uniform clock cycle is as follows. The bit cyclewould be constant, but the waveform for a “1” bit would stay highlonger, say twice as long, as the waveform for a “0” bit. This bearssome resemblance to a phase-shift-keying (PSK) regime.

DCR Circuit's Local Voltage Generation Circuit 110

FIG. 8 is a schematic circuit diagram of an exemplary implementation ofDCR circuit's local voltage generation circuit 110. As mentioned abovein connection with FIGS. 4 and 7, the DCR circuit's local voltagegeneration circuit generates voltages “vdcr,” “vpbias,” “vnbias,” and“vref” for use in other portions of DCR circuit 70.

Voltage “vdcr” is a power supply voltage for use in portions of the DCRcircuit, and is generally commensurate with “vS2” unless qualified bythe assertion of “dcrsleep,” in which case it is pulled low, therebypreventing the DCR circuit from outputting the clock and data signals.When “Vs2” goes to zero, local voltage generation circuit 110 andcomparator circuit 112 are powered down, and “vdcr” also goes to zero,thereby powering down comparator circuit 115. Turning off the power tothese circuits significantly reduces leakage current during the pacingand signal collection phases when it is no longer required to recoverclock and data from “Vs2”. Use of the sleep functionality allows “vdcr”to be set to zero, regardless of “Vs2.” This provides additional powersaving.

Supply voltage “vdcr” is provided at the output of an inverter 170,which receives at an input node 172, the output of a latch 175. Latch175 stores the values of complementary control signals “dcrsleep” and“dcrsleep_b.” When node 172 is at a high voltage, corresponding tosignal “dcrsleep” being asserted, the output signal of inverter 170 iscoupled to the voltage on bus conduction path S1, thus setting supplyvoltage “vdcr” to substantially “ground voltage,” hence turning off thepower supply for the rest of the DCR circuit 70. Alternatively, whencontrol signal “dcrsleep” is de-asserted, as for example during aconfiguration phase, inverter 170 couples power supply voltage “vdcr” to“Vs2,” as averaged or integrated by a capacitor 177.

The DCR circuit's local voltage generation circuit generates the othervoltages using a bias generation circuit 180, When control signal“dcrsleep” is de-asserted, thereby bringing “vdcr” to its high level,bias generation circuitry, the current in a resistor 182 of biasgeneration circuit 180 generates the bias voltage “vpbias,” which isused in current mirrors to generate other bias voltages. For example,reference voltage “vref” is generated by a reflected current in a PMOStransistor 185 flowing through a resistor 187. Similarly, the biasvoltage “vnbias” is generated by the voltage divider formed bytransistors 190 and 192 using another reflected current. As noted above,the reference voltage “vref” is used for recovering data bits from thesignal on bus conduction path S2 during a configuration phase.

Initialization Generation Circuit 75

FIG. 9 is a schematic circuit diagram of an exemplary implementation ofinitialization generation circuit 75. As mentioned above in connectionwith FIG. 6, initialization generation circuit 75 generatesinitialization signals “s2_oneshot_b” and “vhigh_one_shot_b,” which areasserted when the signal on bus conduction path S2 and signal “vhigh”rise above their respective predetermined voltage thresholds. Theinitialization circuit includes signal generation circuits 200 and 205that generate “vhigh_oneshot_b” and “s2_oneshot_b,” respectively.

Consider initially signal generation circuit 200, which generatesinitialization signal “vhigh_oneshot_b” at the output of a three-inputNAND gate 210. When “vhigh” goes from a low voltage to a high voltage,it charges a capacitor 215 through a diode-connected PMOS transistor217. The voltage on capacitor 215 is propagated through five invertingbuffers 221, 222, 223, 224, and 225 to one of the NAND gate's inputs.The other two inputs are connected to “vhigh” and the output from buffer222. The output of buffer 224, when high, charges a capacitor 230.

The voltage “vhigh” powers the buffers and the NAND gate, so when“vhigh” is low, all the buffer outputs are low. When “vhigh” increases,the input to buffer 221 remains low for a short period of time beforecapacitor 215 charges, and the outputs of buffers 221, 222, 223, 224,and 225 will be high, low, high, low, high, respectively. Since theoutput from buffer 222 is low, the NAND gate will be held at a highlevel.

However, as capacitor 215 charges, the input to buffer 221 goes abovethreshold and the output of buffer 221 goes low, the output of buffer222 goes high, and the output of buffer 225 is still high (its inputbeing held low by capacitor 230 while the capacitor charges). Thiscauses the output of NAND gate 210 to go low. Eventually, capacitor 230charges and the output of buffer 224 goes above threshold, causing theoutput of buffer 225 to go low. This causes the output of the NAND gateto go high. So long as capacitors 215 and 230 remain charged, the outputof the NAND gate remains high since buffer 225 continues to provide alow voltage to the NAND gate. Thus, the net effect is to generate adownward pulse when the voltage “vhigh” rises to a high voltage state.

Consider next signal generation circuit 205, which generatesinitialization signal “s2_oneshot_b” at the output of a three-input NANDgate 240. When “Vs2” goes from a low voltage to a high voltage, itcharges a capacitor 245 through a diode-connected PMOS transistor 247.The voltage on capacitor 245 is propagated through five invertingbuffers 251, 252, 253, 254, and 255 to one of the NAND gate's inputs.The other two inputs are connected to “vhigh” and the output from buffer252. The output of buffer 254, when high, charges a capacitor 260. “Vs2”powers buffer 252, while “vhigh” powers the buffers 251, 252, 253, and254, and NAND gate 260. The operation of signal generation circuit 205is substantially the same as that of signal generation circuit 200,which was described above. Thus the operation will not be describedother than to note that the result is a downward pulse when “Vs2” risesto a high voltage state.

Command Interpretation Circuit 80

FIG. 10 is a schematic circuit diagram showing an exemplaryimplementation of command interpretation circuit 80. As mentioned abovein connection with FIG. 6, command interpretation circuit 80 maps thebits in digital data signal “dcr_out” to control commands, and generatescontrol signals including “switch,” “clearb_latch “dcrsleep,” and“dcrsleep_b.” Command interpretation circuit 80 provides the decodeddata bits (“bit15,” delayed by 16 clock periods) of serial data signaldcr_out to electrode control circuit 130.

As shown in FIG. 10, command interpretation circuit 80 includes a 16-bitlong serial shift register 250 formed by 16 serially coupled flip-flops.Not shown in the figure for the sake of clarity is the fact that theseflip-flops, as well as an additional flip-flop 255, derive power attheir respective V+ and V− inputs from “vhigh” and the voltage on busconductor S1, respectively. The flip flops in shift register 250 areclocked by the clock signals “clk” and “clkb” while flip-flop 255 isclocked by these signals but out of phase. This allows the flip-flop toact on the data that was clocked into the shift register during theprevious half cycle.

Predetermined bit patterns in shift register 250 are recognized by adecoding circuit, with a set of NAN gates 261, 262, 263, 264, 26.5, 266,267, and 268 directly receiving one or both of the flip-flop'scomplementary outputs, and a set of NOR gates 271, 272, and 273receiving various combinations of the NAND gate outputs to producecontrol signals “switch,” “clearb_latch,” and the complementary pair ofsleep signals “dcrsleep” and “dcrsleep_b.” Note that the “switch” signaltriggers electrode control circuit 130 to cause one or more specifiedelectrodes to be coupled to either bus conduction path S1 or busconduction path S2.

As mentioned above, after the configuration phase, sleep signals“dcrsleep” and “dcrsleep_b” turn off portions of the satellite chip toconserve power. In one embodiment of the present invention, the Sleepcommand corresponds to bit pattern “0101110000111010.” The signal“dcrsleep” is generated by the output signals of NAND gates 262, 263,265, and 268, and NOR gate 273. Flip-flop 255 latches and holds theoutput of NOR gate 273 to provide the “dcrsleep” and “dcrsleep_b”signals during pacing and/or signal collection phases, during which DCRcircuit 70 is in a turned-off state.

The “clearb_latch” signal is generated in part by the output signals ofNAND gates 265, 266, 267, and 268, which are communicated to NOR gate272. NOR gate 272 is provided to one input of a NAND gate 275, and istriggered by the “vhigh_oneshot_b” initialization signal at the otherinput of NAND gate 275. The “clearb_latch” signal, when asserted, resetsthe registers in electrode control circuit 130, so as to clear thecoupling between the electrodes and bus conduction paths S1 and S2. Inone embodiment of the present invention, the Clear command correspondsto bit pattern “01010011110011010.” In this embodiment, becauserelatively few commands are encoded in a large command space (e.g.,16-bit per command), in all likelihood most bit errors would result in acommand that is not recognized, and thus would not erroneously activateand configure electrodes to result in unintended pacing.

The “switch” signal is generated by the outputs of NAND gates 261, 262,263, and 264, and NOR gate 271. This signal is generated in response todetecting a Switch command for effectuating the configurations specifiedfor the electrodes. In one embodiment of the present invention, theSwitch command corresponds to bit pattern “10101100000110101.”

The “s2_oneshot_b” initialization signal resets all the flip-flops ofshift register 250, when the signal “Vs2” rises to 5 volts. Furthermore,the output bit of the last flip-flop in shift register 250 is providedas output signal “bit15.” Output signal “bit15” allows the received databits to be transmitted to electrode control circuit 130 for electrodeaddress information decoding. A circuit similar to the circuit in FIG.10 is provided in satellite-check circuit 125 to capture a predeterminedbit pattern, which is interpreted as an address of the specifiedsatellite. Satellite selection signals “iamit1” and “iamit2” areasserted when the address matches the stored identity information of thesatellite.

Electrode Control Circuit 130

FIG. 11 is a functional block diagram of an exemplary embodiment ofelectrode control circuit 130. As described above in connection withFIG. 6, electrode control circuit 130 receives control signals fromcommand interpretation circuit 80 and satellite-check circuit 125, anduses these signals to identify and configure the electrodes. Theelectrode control circuit generates output signals “s2 c_p_i,” “s2c_n_i,” and “s1 c_n_i” to control EPAD circuits 135 a, 135 b, 135 c, and135 d, which in turn determine which electrode(s), if any will couple toa given bus conduction path.

In one embodiment of the present invention, control signals “iamit1” and“iamit2” indicate whether or not the local satellite is selected by thesystem. Central controller 10 then sends electrode address informationto the satellite chip. The electrode address information determineswhich of the electrodes under the control of electrode control circuit130 are to be coupled to which of bus conduction paths S1 or S2. Thesystem performs the actual coupling after receiving a “switch” commandfrom central controller 10.

As shown in FIG. 11, electrode-control circuit 130 includes twoidentical electrode register circuits 280 and 285, and four identicalelectrode driver circuits 290 a, 290 b, 290 c, and 290 d. Each ofelectrode register circuits 280 and 285 receives an 8-bit electrodeaddress information word and a corresponding control signal which is oneof identity control signals “iamit1” and “iamit2.” The 8-bit electrodeaddress word and identity control signal are decoded to provide fourpairs of electrode control signals “EnC” and “PnC” (where n is aninteger between 0 and 3 inclusive, identifying one of electrode drivercircuits 290 a, 290 b, 290 c, and 290 d). These electrode drivercircuits drive EPAD circuits 135 a, 135 b, 135 c, and 135 d,respectively (shown in FIG. 6, and in more detail below in FIG. 14).

In this implementation, for example, electrode register circuit 280provides its 8-bit electrode address information word as controlssignals E0C, P0C, E1C, P1C, E2C, P2C, E3C, and P3C, respectively, whencontrol signal “iamit2” is asserted. Control signals E0C and P0C arereceived into electrode driver circuit 290 a and denote whether or notelectrode driver circuit 290 a (and hence its corresponding electrodealso) is enabled and its polarity, respectively. Similarly, electrodedriver circuit 290 a receives another pair of these control signals fromelectrode register 285. Based on these four control signals(corresponding to signals internally denoted in each electrode drivercircuit as “enable1_b,” “enable2_b,” “s2connect1_b,” and“s2connect2_b”), control signals “s2 c_p_i,” “s2 c_n_i,” and “s2 c_n_i”are provided to control the switching of a corresponding electrode.

One advantage of this design for electrode control circuit 130 is thatit allows a selected electrode to be coupled to bus conduction path S1,according to the control signals from electrode register circuit 280,for example. It also allows another selected electrode to be coupled tobus conduction path S2, according to the control signals from electroderegister 285. In this manner, one electrode sources current into thetissue, while a another electrode sinks current from the tissue. Thisarrangement allows the pacing system to focus the pacing current to aspecific tissue area. In contrast, a pacing system without acurrent-sink electrode may suffer from diffusing current over a largetissue volume and unsatisfactory pacing accuracy and efficacy.

While one-wire embodiments would not supply pacing signals betweenelectrodes on the same satellite, the ability to allow any electrode tobe coupled to either bus conduction path nevertheless providesflexibility. Further, as noted above, pacing pulses may still be appliedbetween a satellite electrode and the pacing can through the subject'sbody in two-wire embodiments as well as in one-wire embodiments.

Electrode Control Circuit 130's Electrode Register Circuits 280, 285

FIG. 12 is a circuit schematic of an exemplary implementation for anelectrode register circuit (e.g., one of electrode register circuits 280and 285). The electrode register circuit includes a shift register 300and a parallel register 305, each comprising eight flip-flops. Theflip-flops in shift register 300 are serially coupled and store theincoming data bits in order. Each flip-flop in register 305 loads theoutput bit of a corresponding flip-flop in the shift register wheneverthe “switch” signal is asserted. (A previous assertion of signal“clearb_latch” resets the output bits of register 305 to logic value“0.”) The “switch” signal is gated (NAND gate 310) by the identitycontrol signal it receives (e.g., control signal “iamit1,” if theelectrode register circuit implements electrode register 280). In thisway, only the correct electrode address information is received byregister 305 and is provided as control signals to electrode drivercircuits.

Electrode Control Circuit 130's Electrode Driver Circuits 290 a, 290 b,290 c, 290 d

FIG. 13 is a schematic circuit diagram of an exemplary implementation ofany one of electrode driver circuits 290 a, 290 b, 290 c, and 290 d. Theelectrode driver circuit receives signals “enable1_b,” “enable2_b”“s2connect1_b,” and “s2connect2_b,” which correspond to signals EnC andPnC from electrode registers in electrode register circuits 280 and 285,respectively. These input control signals are decoded to provide controlsignals “s1connect_n,” “s2connect_n,” and “s2connect_p” according to atruth table, which is provided in the following TABLE 1 Input enable1_b1 0 X 0 0 X X enable2_b 1 X 0 X X 0 0 s2connect1_b X 1 1 0 X 0 X Outputs2connect2_b X 1 1 X 0 X 0 s2connect_p 1 1 1 0 0 0 0 s2connect_n 0 0 0 11 1 1 s1connect_n 0 1 1 0 0 0 0 EPAD Action (bus Not S1 S1 S2 S2 S2 S2conduction path to which coupled electrode is coupled)

Signals “s1connect_n” and “s2connect_n” assume voltage valuescorresponding to “vhigh” or 0, while signal “s2connect_p” assumesvoltage values of “Vs2” or 0. As mentioned above, “vhigh” is used tomaintain the electrode register state during times when the satellitechip is not receiving bus power. In principle, only the flip-flops inparallel register 305 need be maintained, i.e., preserving the values ofE0C, P0C, E1C, P1C, E2C, P2C, E3C, and P3C. In a current implementation,however, all the flip-flops are kept energized so that the shiftregisters don't come up in an unknown state.

EPAD Circuits 135 a, 135 b, 135 c, and 135 d

FIG. 14 is a schematic circuit diagram of an exemplary implementation ofone of the electrode pad (EPAD) circuits shown in FIG. 6. The circuit isdrawn separately (and identically) in right and left portions of thefigure. The right portion shows current paths for various scenarios, andthe reference numerals have been removed for clarity.

The particular mapping shown in Table 1 is designed for the particularEPAD circuit shown in FIG. 14. In Table 1, the values (1, 0, 0), (1,0, 1) and (0, 1, 0) for signal combination (“s2connect_p”,“s2connect_n”, s1connect_n”) encode instructions to leave the specifiedelectrode uncoupled, to couple the specified electrode to bus conductionpath S1, and to couple the specified electrode to bus conduction pathS2, respectively.

In the EPAD circuit, a low voltage at signal “s2connect_p” couples theelectrode to bus conduction path S2 through a PMOS transistor 320. Ahigh voltage at signal “s2connect_n” couples the electrode to busconduction path S2 via an NMOS transistor 322. A high voltage at signal“s1connect_n” couples the electrode to bus conduction path S1 via anNMOS transistor 325. Thus, the values (1, 0, 0), (0, 1, 0) and (1, 0, 1)for signal combination (“s2connect_p”, “s2connect_n” s1connect_n”)decouples the electrode from S1 and S2, couples the electrode to S2, andcouples the electrode to S1, respectively.

The right portion of FIG. 14 shows current paths between the electrodeand the selected bus conduction path. The different paths are designated“Pacing A,” “Pacing B,” “Sampling A,” and “Sampling B,” depending on theconduction path and the reason for coupling the electrode to the busconduction path.

For those one-wire embodiments where there is no dedicated fifthelectrode to contact the subject's body fluid, one of electrodes 100 a .. . 100 d is used to provide “Vs2” to the chip circuitry. This electrodecannot be coupled to bus conduction path S1. This is shown as the path“Sampling A” and “Vs2” is a diode drop below the voltage at theelectrode due to the driver transistor whose gate is at the lowerpotential “Vs2” compared to the electrode.

System Operation

In a specific embodiment, the configuration and control commandstructure is as follows. The Sleep command generates sleep signals“dcrsleep” and “dcrsleep_b,” which turn off DCR circuit 70 at times whenthere are no data or clock signals that need to be recovered from thebus. The Clear command generates the control signal “clearb_latch” forclearing the flip-flops in parallel register 305. The Switch commandgenerates the control signal “switch,” which loads the values in shiftregister 300 into parallel register 305. The Switch command is onlyissued following the transmission of address and configurationinformation. The current architecture supports configuring any twosatellites with a single Switch command.

More particularly, the central controller communicates two satelliteidentification octets for the two satellites to be configured, followedby two configuration octets representing electrode switching states forthe addressed satellites, followed by the Switch command. The serial bitstream from DCR circuit 70 passes through 16-bit shift register 250 incommand interpretation circuit 80, thereafter into the two 8-bit shiftregisters 300 in electrode register circuits 280 and 285, and finallyinto two similar 8-bit shift registers (not separately shown) insatellite check circuit 125. Thus, when all the bits for the twosatellite identification octets, followed by the two configurationoctets, followed by the Switch command have been read in, the satelliteidentification octets are in the satellite check circuit shiftregisters, the configuration octets are in shift registers 300 inelectrode register circuits 280 and 285, and the Switch command bits arein shift register 250 in command interpretation circuit 75.

Thus satellite check circuit 125 is in a position to match eachsatellite identification octet against that satellite's hard-codedidentification and issue the “iamit1” and “iamit2” control signalssignifying a match, electrode register circuits 280 and 285 are have theconfiguration octets in their shift registers, and commandinterpretation 80 is in a state where the 16 bits in its shift register,when decoded signify that they represent the switch command. Thus, eachsatellite can determine whether it is one of the satellites to beconfigured, and if so, allows the “switch” signal to be passed throughto load the contents of shift register 300 into parallel register 305.

FIG. 15 is a flow chart illustrating an exemplary configuration(programming) process followed by a cardiac pacing or monitoringprocess. The flow chart has a left portion showing the operation fromthe point of view of central controller 10, and middle and rightportions showing the operation from the point of view of the satellites.The flow chart shows the operations in a particular order, which is anabstraction. As discussed above, the serial nature of the particularhardware architecture is that the satellite information, the electrodeconfiguration information, and the switch command are passing throughthe various shift registers and don't represent the operative stateuntil the last bit has been read into the command interpretation shiftregister.

The central controller commences the process by raising the voltage onbus conductive path S2 (step 340), in response to which the satelliteswake up their DCR circuits (step 355), so as to be able to accept andprocess digital data. In some cases the sends the Clear command (step350), in response to which the satellites clear their registers (step355). This is optional, but is usually done, especially when configuringmore than two satellites.

The central controller initiates a configuration phase by sendingsatellite address information (step 360), and the satellites receivethis information (step 365). In the specific implementation, thisentails clocking the serial bit stream into the command interpretationcircuit's shift register, which is not the final destination. Rather,the satellite address data is only available in the satellite checkcircuit's registers after subsequent data is sent and received.

The central controller then sends electrode configuration information(step 370) and the satellites receive this information (step 375). Thecentral controller then sends the Switch command (step 380) and thesatellites receive this command. Each satellite then determines whetherthe received address information matches that satellite's storedsatellite address information (branch 390). Those satellites for whichthe received address information matches that satellite's storedsatellite address information (i.e., at least one of control signals“iamit1” and “iamit2” is asserted) store the configuration in theirregisters (step 395) and set their switches (step 400) to couple theappropriate electrode(s) to the appropriate bus conduction path(s).Steps 360, 370, and 380 (and the responsive steps 365, 375, 385, 390,395, and 400) may be repeated depending on the number of satellites thatare to be configured.

The central controller then sends the Sleep command (step 405), inresponse to which the satellites turn off their DCR circuitry whileretaining stored configuration information (step 410). The centralcontroller then enters a pacing or sensing phase by sending pacingpulses or floating the bus conductive paths and activating sensingcircuitry to sense analog signals using the configured electrodes (step415). Depending on the type of phase, the satellites pass the pacingpulses from the bus to the electrode(s) or pass the analog signals fromthe electrodes to the bus (step 420). In most cases, the satellites donot need to perform any particular actions during these phases. Manysensing and pacing phases can be implemented between two consecutiveelectrode configurations. For example, after a configuration iscompleted, the central controller can sense the impedance betweenelectrodes to verify that the electrodes are properly configured orremains properly configured before each pacing commences.

Exemplary Sensing Application

Because embodiments of the present invention provide exceptionalflexibility, various applications beyond cardiac pacing are nowpossible. One such application is the measurement of the speed at whicha depolarization wave propagates within the tissue. The precisemeasurement of signal conduction velocity can be very useful inassisting other forms of treatments. For example, the ideal dosage ofcertain medication can be assessed by monitoring different tissueconduction velocities.

It is understood that some medications which are often prescribed tocardiac patients can change the conduction velocity of a depolarizationsignal propagating in the cardiac tissue. The conduction velocity withinthe tissue can be used as a feedback measurement for titration ofvarious medications such as beta blockers. Without proper titration, asub-optimal dosage of medication may result in the heart not contractingenough or contracting too much. Embodiments of the present inventionmake accurate titration possible. Typically, the propagation delay of adepolarizing signal is much slower (e.g., in the order of milliseconds)than the time required to reconfigure the electrodes (e.g., in the orderof microseconds). Note that for conduction-velocity detection purposes,a depolarizing signal is preferred over a signal with a single polaritywhich uses the patient's body as a current sink. A depolarizing signalis more resistant to interferences and can be localized more accurately.Detection of such a depolarizing signal is possible in embodiments ofthe present invention because two electrodes within the same satellitecan be configured as a pair of bipolar electrodes.

In one exemplary process for measuring conduction velocity usingsatellites, the electrodes in satellites at different locations alongthe signal's propagation path may be successively configured to sensethe depolarization wave. The conduction velocity may be calculated fromthe time at which each satellite senses the passing of depolarizationwave. The measured conduction velocity can be used to determine theeffectiveness of the medicine or to formulate an effective dose.

More specifically, to detect a depolarizing signal (naturally occurringor induced) the system transmits necessary commands and data toconfigure a first satellite so as to create a pair of bipolar receivingelectrodes on the first satellite. When the depolarizing signal reachesthe first satellite, the signal is received by the bipolar electrodesand the receiving time is recorded. After recording the time at thefirst satellite, the system subsequently transmits another set ofinformation to configure a second satellite so as to create a pair ofbipolar receiving electrodes on the second satellite. When thepropagating signal reaches the second satellite, the system receives thesignal and records the corresponding time. Based on the respective timesat which the first and second satellites detect the signal, the systemcan calculate the propagation delay between the two satellites, andbased on the separation of the satellites, can calculate the signal'sconduction velocity.

Another application allows a large number of sensing phases to beprovided over a very short period of time between configuration phasesinvolving different combinations of electrodes in the satellites. Suchrapid sensing and reconfiguration allows a signal map be drawn over thatshort period of time for any major electrical event in the vicinities ofthe satellites in the lead.

Two-Wire Programming and Pacing

FIG. 16A is a schematic representation of programming and pacing with atwo-wire embodiment of the invention. The figure shows centralcontroller 10 and a single satellite, designated 20 (it could be any ofsatellites 20 a . . . 20 d in FIG. 2). The central controller and thesatellite have corresponding S1 and S2 terminals (nodes), and theconnection between the central controller and the satellite is throughtwo bus conduction paths having dedicated conductors that are insulatedfrom the subject's body. The left portion of the figure shows thecurrent path for programming the satellite. The current flow is shownschematically by a curved arrow, and the path is from the centralcontroller's S2 node along the upper conductor to the satellite's S2node, through the satellite's internal circuitry (the conduction path isshown as a dashed line), back from the satellite's S1 node along thelower conductor to the central controller's S1 node.

The middle and right portions of the figure show two pacing regimes. Forthe regime shown in the middle portion of the figure, the satellite isconfigured so that electrode 102 b is connected to the upper conductionpath and electrode 102 c is connected to the lower conduction path. Thecurrent flow is shown schematically by a curved arrow, and the path isfrom the central controller's S2 node along the upper conductor to thesatellite's S2 node, along a low-impedance path through the satellite'sswitches to electrode 10 b, through the subject's body to electrode 100c, through an additional low-impedance path through the satellite'sswitches to the satellite's S1 node (the low-impedance conduction pathsthrough the satellite are shown as solid lines), back from thesatellite's S1 node along the lower conductor to the centralcontroller's S1 node. Thus the pacing current is caused to flow througha small region of tissue between electrodes 102 b path and 102 c.

The right portion shows a regime where the central controller's S2 nodeis disconnected from the upper conductors and connected to the outsideof the controller (pacing can). As shown, the satellite is configured sothat electrode 100 c is connected to the lower conductor so the currentflows from the central controller's S2 node to the outside of the can,through the subject's body to electrode 100 c, through a low-impedancepath through the satellite's switches to the satellite's S1 node (thelow-impedance conduction path through the satellite is shown as a solidline), back from the satellite's S1 node along the lower conductor tothe central controller's S1 node. In this regime, it would also bepossible to have multiple electrodes connected to the lower conductor,although for a cylindrical electrode arrangement as shown in FIG. 3, theconnections would likely be to no more than the two electrodes that areclosest to the tissue to be stimulated.

One-Wire Embodiments

If other signals are not carried on bus conduction path S2, busconduction path S2 may be eliminated and the subject's body fluids maybe used as a power and data conductor. This is described in additionaldetail in the above referenced U.S. Provisional Patent Application No.60/607,280, filed Sep. 2, 2004, titled “One Wire Medical Monitoring andTreating Devices.”

For example, in the circuit described in FIG. 2, a single wire S1connects central controller 10 with the S1 terminal on satellite units20 a, 20 b, . . . . The satellite units' S2 terminals may be connectedto an electrode on the satellite unit (electrode 105 FIG. 3) thatcontacts the body tissue. A conduction path is then established betweenthe outer surface of the pacing can, the body tissue, the electrode, andS2. Coupled with S1, these two conduction paths form a loop throughwhich power and data may data may be transmitted. Initially, this looprepresents a relatively high impedance loop (100's of kilo-ohms) throughwhich relatively low currents are able to flow. These currents are wellbelow that required to stimulate tissue (for example 10's ofmicro-amps). In this state, these very low currents are used to transmitdata to the satellite units where the data is stored.

This stored data is then used to control relatively very low impedancetransistors between selected electrodes and S1. Once these switches areenabled, a relatively low impedance loop (100's of ohms) is establishedthrough which much higher levels of current are able to flow. It isthese much high levels of current that are used to stimulate tissue nearthe selected electrodes. The selected electrodes through the enabledtransistors are also used allow relatively low current and low potential(less than the threshold current of the switch transistor) signals topass with low additional noise back to the central controller where theyare compared to the potential on the surface of the can that houses thecentral controller (or other electrode), amplified and digitized for useby the rest of the system. It is one of the teachings of this inventionthat the enabled switches are able to maintain their function (eitherhigh impedance or very low impedance) while the conduction loop is notproviding power to the satellite unit.

In the implementation with a fifth electrode 105 (see FIG. 3) connectedto the satellite chip's S2 terminal, the current for programming thedevice flows in a loop described by: Drive electronics in can>S1 (theone-wire going down the lead)>Chip as Vss>Vdd>S2>electrode contactingthe blood>Outer surface of the pacing can>Drive electronics.

As mentioned above, electrode 105 is optional. In an implementationwhere there is no fifth electrode, and S2 is only an internal node onthe chip, no external connection is made to S2. In this embodiment,leakage current from one or more electrodes to internal node S2 issufficient to charge up “vhigh” and also sufficient to sendcommunication signals to the DCR. Once the signals are sent, theswitches selectively connecting some—but not all—of the electrodes to S1are set. Then, the pacing current can flow from the can, through theselected electrode, to S1, and back to the can. In the mode where thecentral controller is sending data, but not pacing, the chip presents ahigh-impedance path to current and signals are sent in this loop:Can>blood/tissue>Electrodes>S1 via diode-connected CMOS inEPAD>circuitry>S1>electronics in Can.

Once the switches are set, the chip creates a low impedance connectionbetween one or more of the electrodes and S1 and the primary currentloop becomes: Can>Blood/tissue>Electrodes>to S1 via set switch onchip>S1>can. When resetting the switch connections or clearing them,both current loops exist simultaneously. One “feature” of thisembodiment is that not all four electrodes may be connected to S1—onemust be left as a diode-connected CMOS switch for supplying “Vs2” to thecircuit.

One-Wire Programming and Pacing

FIG. 16B is a schematic representation of programming and pacing withtwo one-wire embodiments of the invention. The left and middle portionsof the figure show a central controller and a single satellite,designated 20′ in that it differs from satellites 20 a . . . 20 d inFIG. 2 by virtue of having the optional fifth electrode 105. The centralcontroller and the satellite have corresponding S1 and S2 terminals(nodes). The connection between the central controller's S1 node and thesatellite's S1 node is through a bus conduction path having a dedicatedconductor that is insulated from the subject's body. However, there isno dedicated conductor between the central controller's S2 node and thesatellite's S2 node. Rather, the central controller's S2 node connectedto the outside of the controller (pacing can) and the satellite's S2node is connected to dedicated electrode 105, which contacts thesubject's body. Thus the second conduction path includes and is in largepart defined by the subject's body.

The left portion of FIG. 16B show programming the satellite. This caseis analogous to the case of programming the two-wire embodimentdiscussed in connection with the left portion of FIG. 16A except thatthe subject's body substitutes for the upper dedicated conductor. Themiddle portion of FIG. 16B show pacing, and this is exactly like thesecond example shown in the right portion of FIG. 16A.

The right portion of FIG. 16B shows the embodiment where there is nodedicated electrode for the second bus conduction path (S2). Rather, thesatellite's S2 node is not associated with any particular electrode.Programming is accomplished by establishing a path between one of theelectrodes, say electrode 100 a, and the satellite's S2 node.Programming then proceeds, but it is not possible to specify anydifferent state for electrode 100 a.

Additional Embodiments (AC Signals, Hybrid Conduction Paths)

FIG. 17 of a block diagram of a satellite adapted from the previouslydescribed embodiments to receive and process AC signals over the bus.The satellite circuitry is denoted with the reference numeral 60′ tosignify that it corresponds to satellite circuitry 60 shown in FIGS. 2and 5 (as well as the more detailed circuit schematics). In short, thesatellite circuitry includes a rectifier 450, shown as a diode bridge,and a capacitor 455, which may not be needed. The satellite is shown ashaving two terminals, drawn as larger black dots, designated R1 and R2that are coupled to the bus and provide the inputs to rectifier 450. Therectified output nodes are designated S1 and S2 with S2 being at thehigher DC voltage. The rectified output signal can be applied to theremaining portions of the satellite circuitry, which may besubstantially identical to the embodiments described in previoussections.

FIG. 18 is a timing diagram showing how the AC signal may be configuredso that, when rectified, it would generally match the modulated signalshown in FIG. 4. In the particular implementation, different bit valuesare represented by different periods for a square wave. Also, in theparticular implementation, the modulation is between 4.5 volts and 5volts. The timing diagram includes an upper portion showing the ACvoltage, and a lower portion showing the rectified voltage. Theparticular example is a “0” bit followed by a “1” bit. As can be seen,the “0” bit is achieved by rectifying one cycle having an amplitude of 5volts followed by one cycle having an amplitude of 4.5 volts. The “1”bit is achieved by rectifying two cycles having an amplitude of 5 voltsfollowed by two cycles having an amplitude of 4.5 volts.

FIG. 19 shows satellite 60′ incorporated into a system using hybridconductive bus paths. The central controller is designated 10′signifying that it generally corresponds to previously described centralcontroller 10. Each bus conduction path includes a first portion 460provided by an insulated conductor, a second portion 465 provided by adedicated conductor and/or electrode and/or mesh (for example adefibrillation-type electrode) that is not insulated from the subject'sbody, and a third portion 470 that is provided by the subject's bodyfluids and/or tissue.

Thus, the current loop would begin at the controller electronics,through an insulated wire, through an uninsulated wire and/or electrodeand/or mesh, through body tissue, through a wire or electrode, to thesatellite's R2 input, through the satellite's circuitry, through thesatellite's R1 input, through body fluids and/or tissue, through anuninsulated wire and/or electrode and/or mesh, through an insulated wireand back to the controller electronics.

The satellite is shown with electrodes R1 and R2 that contact the bodyat some distance apart, this distance in many ways defining theefficiency of power transmission. The satellite is also shown with four(for example) electrodes that are programmed to be connected to eitherof the satellite's S1 or S2 nodes (or disconnected from both). Toprogram this satellite, the pacing can/controller would first place theprogramming code onto a high-frequency carrier signal (high enough thatthe signal cannot cause pacing at the broadcast voltage) and broadcastthis signal between the two electrodes contacting the body fluid and/ortissue. The circuitry on the satellite would first rectify the AC signalinto a DC signal. This signal would then go into circuitry substantiallysimilar to that described above to control which electrodes would beconnected or disconnected to S1 or S2.

An example of how this might be used clinically is for conductive pathportion 465 a to be or terminate in a defibrillation coil implanted inthe right ventricle and conductive path portion 465 b to be or terminatein a metal mesh implanted subcutaneously under the skin over the heart.The satellite might, for example, be mounted on a stent (producing a“satellite-stent”) that is placed for therapeutic reasons into thecoronary artery. The satellite would have two electrodes R1 and R2 thatare some distance apart to pick up the AC signal from the defibrillationcoil and the implanted mesh. The satellite would have two otherelectrodes that may be programmed to be connected to S1 and S2, forminga bipolar electrode pair. When they are programmed to be connected, ahigh frequency signal imposed between the defibrillation coil and themesh will cause a DC voltage to appear across the bipolar electrodes.This DC voltage will “capture” the myocardial tissue. In operation, this“pacing-stent” may be first used to try to defibrillate the heart beforeusing up a lot of power to defibrillate the customary way. Multiplepacing-stents might be used simultaneously for this purpose.

Another variation of the satellite-stent is as it is used with othertypes of effectors, such as pressure sensors that would determine ifrestenosis has partially occluded the “satellite-stent.” The“active-stent” would then emit a code that is representative of thepressure through the electrodes that are connected to S1 and S2, perhapsusing a different carrier frequency. This signal would then be picked upby a pair of nearby (which may be the same or nearby the same electrodesthat broadcast the first AC signal).

AC embodiments such as this may improve the reliability of the“one-wire” and “two-wire” embodiments, as well, be reducing thecorrosion that might appear between the two wires or the one-wire andthe body.

Terminology

Some embodiments of the present invention provide multiplexed carrierdevices and systems, and methods for configuring and using multiplexedcarriers. By “multiplexed” or “multiplexing,” it is generally meant thata carrier may carry two or more effectors which may transmit and/orreceive signals to and/or from one or more “remote” devices. A remotedevice may be located anywhere, either on the carrier or apart from thecarrier. Central controller 10 is, from the point of view of thesatellite, a remote device.

Generally, multiplexing may be accomplished by any of a number ofdifferent techniques. One technique, for example, may be referred togenerally as “broadcasting.” A second multiplexing technique may bereferred to as “frequency-domain multiplexing.” A third exemplarymultiplexing technique may be referred to as “time-domain multiplexing.”Other multiplexing techniques involve addressing, whereby each effectorhas a digital address or number. Any of these techniques, or any othersuitable techniques, may be used in a multiplexed carrier of theinvention. In some embodiments, for example, combinations of the abovedescribed techniques may be used, such as a combination offrequency-domain and time-domain multiplexing.

The term “effectors” is generally used herein to refer to sensors,actuators, sensor/actuators, or any other device that may be coupledwith a carrier for performing a function. In some embodiments, forexample, the at least two identifiable effectors comprise a transducerand a processor (digital or analog), where the processor is identifiableand distinguishable from all other effector processors usingconventional multiplexing circuitry.

The effectors may be intended for collecting data, such as but notlimited to pressure data, volume data, dimension data, temperature data,oxygen or carbon dioxide concentration data, hematocrit data, electricalconductivity data, electrical potential data, pH data, chemical data,blood flow rate data, thermal conductivity data, optical property data,cross-sectional area data, viscosity data, radiation data and the like.Alternatively, the effectors may be intended for actuation orintervention, such as providing an electrical current or voltage,setting an electrical potential, heating a substance or area, inducing apressure change, releasing or capturing a material or substance,emitting light, emitting sonic or ultrasound energy, emitting radiationand the like.

In some embodiments, both sensor(s) and actuator(s) may be coupled witha carrier. In one embodiment, at least some of the effectors include atransducer and an electronic conversion circuit, wherein output from thetransducer is encoded using a carrier frequency and broadcast onto oneof the electrical conductors, and wherein each effector utilizes adifferent carrier frequency. Alternatively, at least some of theeffectors may include a transducer and an electronic conversion circuit,wherein output from the transducer is broadcast onto one of theelectrical conductors during a specified time interval, and wherein eacheffector utilizes a different time interval.

The data collected may include any one of pressure data, volume data,dimension data, temperature data, oxygen or carbon dioxide concentrationdata, hematocrit data, electrical conductivity data, electricalpotential data, pH data, chemical data, blood flow rate data, thermalconductivity data, optical property data, cross-sectional area data,viscosity data, radiation data and the like. Typical methods will beperformed where the sensors are distributed and the catheter present inthe vasculature and/or within a chamber of the heart. Other methods willbe performed where the sensors are distributed on a flat surface and thesurface is present on or near brain tissue. Still other methods will beperformed where the sensors are distributed and the catheter present inthe urinary tract, reproductive tract, endoscopic surgical site,abdominal cavity, gastrointestinal tract or a joint space.

The effectors may be mounted to a surface of the carrier or may bedisposed within the body of the carrier. In various embodiments, suchmultiplexed carriers may be used for sensing any of a variety of data,such as pressure data, volume data, dimension data, temperature data,oxygen or carbon dioxide concentration data, hematocrit data, electricalconductivity data, electrical potential data, pH data, chemical data,blood flow rate data, thermal conductivity data, optical property data,cross-sectional area data, viscosity data, radiation data and the like.

Alternatively, the effectors may be intended for actuation orintervention, such as providing an electrical current or voltage,setting an electrical potential, heating a substance or area, inducing apressure change, releasing or capturing a material, emitting light,emitting sonic or ultrasound energy, emitting radiation and/or the like.Carriers may also be used in a variety of locations within a body, suchas in one or more chambers of the heart, in arterial or venousvasculature, in or on brain tissue, in the urinary, gastrointestinal orreproductive tracts, in the abdominal cavity, in a joint space or thelike.

CONCLUSION

In conclusion, it can be seen that embodiments of the present inventionmay provide one or more of the advantages mentioned above or discussedbelow.

The exemplary control circuit described above allows several uniquefeatures and functions to be implemented in a cardiac pacing/signaldetection system. One such feature is that the system can address andindividually pace through the two bus conduction paths residing within apacing lead. In addition, the system can collect unamplified analogsignals through the satellite electrodes over the same two wires. Thisfeature significantly reduces the complexity of the system and providesunprecedented flexibility which has not been available in conventionalpacing systems.

Another advantage of the embodiments of the satellite circuitry is that,by using specifically designed digital logic, the system can providepower supply and facilitate digital communication simultaneously overthe two bus conduction paths. Specifically, the satellite circuitry canextract a DC power supply, derive a clock signal, and capture themodulated bit sequences at the same time. Furthermore, the specialinitialization generation circuit ensures that during a power-up period,each satellite is not misconfigured by accident.

In addition, embodiments of the satellite circuitry can result in anextremely low power consumption. This is because the unique functions ofthe satellite circuitry are implemented with special device-leveldesigns to minimize leakage current. For example, exemplary satellitecircuitry may adopt specific CMOS designs with long gate lengths toreduce the amount of leakage current through the gates. Additionally,embodiments of the satellite circuitry may have extra substrate contactsand vias. Because of these low-leakage-current design features, asignificant portion of the control circuit can be turned off between twoconsecutive recharges while the circuit remains in a configured state.

While the above is a complete description of specific embodiments of theinvention, the above description should not be taken as limiting thescope of the invention as defined by the claims.

1-46. (canceled)
 47. An integrated circuit for use to configureelectrodes in an implanted lead, the implanted lead being operativelycoupled to a controller, the integrated circuit comprising: a firstterminal; a second terminal; and circuitry coupled to the first andsecond terminals wherein, during a first time interval, during whichdigital configuration signals are provided from the controller on thefirst terminal, the circuitry selectively configures selected ones ofthe electrodes to the first terminal, and wherein, during a second timeinterval, the controller administers electrical signals through theconfigured electrodes by way of the first terminal.
 48. The integratedcircuit of claim 47, wherein, during a third time interval, thecontroller senses electrical signals in the vicinities of the configuredelectrodes by way of the first terminal.
 49. The integrated circuit ofclaim 47, wherein the first terminal is coupled to a conductor providedin the implanted lead.
 50. The integrated circuit of claim 47, whereinthe second terminal is coupled to a conductor provided in the implantedlead.
 51. The integrated circuit of claim 47, wherein the first terminalis coupled to a conductive fluid into which the lead is implanted. 52.The integrated circuit of claim 47, wherein the second terminal iscoupled to a conductive fluid into which the lead is implanted
 53. Theintegrated circuit of claim 52, wherein the power supply circuitgenerates provides the power supply voltage during the second timeinterval from energy collected during the first time interval
 54. Theintegrated circuit of claim 47, wherein the configuration signals areencoded using a signal modulation convention.
 55. The integrated circuitof claim 54, wherein the signal modulation convention comprises afrequency-shift keying signal modulation convention.
 56. The integratedcircuit of claim 47, wherein the control circuit comprises memoryelement for enabling the selected electrodes to remain configured duringthe second time interval.
 57. The integrated circuit of claim 47,wherein the integrated circuit is assigned an identity code, and whereinthe configuration signals are received into the integrated circuit onlywhen the identity code matches a bit sequence in the configurationsignals.
 58. The integrated circuit of claim 47, wherein portions of thecontrol circuit are configured to go into a low power mode of operationduring the second time interval.
 59. The integrated circuit of claim 47,wherein the number of commands encoded in the configuration signals hasa predetermined number in bits, considerably less than the total numberof commands encodable in the predetermined number of bits.
 60. Theintegrated circuit of claim 47, wherein the control circuit generates anasynchronous reset signal to clear the configurations of the selectedelectrodes at the beginning of the first time interval.
 61. Theintegrated circuit of claim 47, wherein the control circuit comprises aclock recovery circuit which recovers a clock signal from theconfiguration signals.
 62. The integrated circuit of claim 47, whereinthe selected electrodes are configured upon receiving a switch commandin the configuration signals.
 63. The integrated circuit of claim 47,wherein the control circuit comprises multiple electrode configurationcircuits each provided to configure an associated electrode.
 64. Theintegrated circuit of claim 63, wherein a plurality of like integratedcircuits are provided at various locations in the embedded lead.
 65. Theintegrated circuit of claim 64, wherein selected electrodes in one ofthe like integrated circuits are configured to couple to the firstterminal and selected electrodes in another of the like integratedcircuits are configured to couple to the second terminal. 66-75.(canceled)